HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 214

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Direct Memory Access Controller (DMAC)
9.5
1. Access is possible regardless of the DMA channel control register (CHCR0 to CHCR3) data
2. When rewriting the RS0–RS3 bits of CHCR0–CHCR3, first clear the DE bit to 0 (set the DE
3. When an NMI interrupt is input, the NMIF bit of the DMAOR is set even when the DMAC is
4. Set the DME bit of the DMAOR to 0 and make certain that any DMAC received transfer
5. Do not access the DMAC, DTC, BSC, or UBC on-chip peripheral modules from the DMAC.
6. When activating the DMAC, do the CHCR or DMAOR setting as the final step. There are
7. After the DMATCR count becomes 0 and the DMA transfer ends normally, always write a 0 to
8. Designate burst mode as the transfer mode when using the address reload function. There are
9. Designate a multiple of four for the TCR value when using the address reload function. There
10. When detecting external requests by falling edge, maintain the external request pin at high
11. When operating in single address mode, establish an external address as the address. There are
12. Do not access DMAC register empty addresses (H'FFFF86B2 to H'FFFF86BF). Operation
13. If DMAC transfer is aborted by NMI or AE setting, or DME or DE2 clearing, during DMAC
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REJ09B0273-0500
size. Other than the DMA operation register (DMAOR) accessing in byte (8 bit) or word (16
bit) units, access all registers in word (16 bit) or longword (32 bit) units.
bit to 0 before doing rewrites with a CHCR byte address).
not operating.
request processing has been completed before entering standby mode.
instances where abnormal operation will result if any other registers are established last.
the TCR, even when executing the maximum number of transfers on the same channel. There
are instances where abnormal operation will result if this is not done.
instances where abnormal operation will result in cycle steal mode.
are instances where abnormal operation will result if anything else is designated.
level when performing the DMAC establishment.
instances where abnormal operation will result if an internal address is established.
cannot be guaranteed when empty addresses are accessed.
execution with address reload on, the SAR2, DAR2, and DMATCR2 settings should be made
before reexecuting the transfer. The DMAC will not operate correctly if this is not done.
Cautions on Use