HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 665

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

21.2.2
The system control register (SYSCR) is an 8-bit readable/writable register that enables or disables
accesses to the on-chip RAM.
SYSCR is initialized to H'01 by the rising edge of a power-on reset.
Bits 7 to 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 0—RAME Enable (RAME): Selects enabling or disabling of the on-chip RAM. When
RAME is set to 1, on-chip RAM is enabled. When RAME is cleared to 0, on-chip RAM cannot be
accessed. In this case, a read or instruction fetch from on-chip RAM will return an undefined
value, and a write to on-chip RAM will be ignored. The initial value of RAME is 1.
When on-chip RAM is disabled by clearing RAME to 0, do not place an instruction that attempts
to access on-chip RAM immediately after the SYSCR write instruction, as normal access cannot
be guaranteed in this case.
When on-chip RAM is enabled by setting RAME to 1, place an SYSCR read instruction
immediately after the SYSCR write instruction. Normal access cannot be guaranteed if an on-chip
RAM access instruction is placed immediately after the SYSCR write instruction.
Bit 0: RAME
0
1
Initial value:
System Control Register (SYSCR)
R/W:
Bit:
Description
On-chip RAM disabled
On-chip RAM enabled (initial value)
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
Rev. 5.00 Jan 06, 2006 page 645 of 818
—
R
3
0
Section 21 Power-Down State
—
R
2
0
REJ09B0273-0500
—
R
1
0
RAME
R/W
0
1