HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 429

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes
2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
Figure 13.12 shows an example of SCI receive operation in the multiprocessor format.
that the transmit data register (TDR) contains new data, and loads this data from the TDR into
the transmit shift register (TSR).
transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the
SCI requests a transmit-data-empty interrupt (TxI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a.
b.
c.
d.
e.
from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then
continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE)
in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
Start bit: one 0 bit is output.
Transmit data: seven or eight bits are output, LSB first.
Multiprocessor bit: one multiprocessor bit (MPBT value) is output.
Stop bit: one or two 1 bits (stop bits) are output.
Marking: output of 1 bits continues until the start bit of the next transmit data.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 06, 2006 page 409 of 818
REJ09B0273-0500