HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 212

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Direct Memory Access Controller (DMAC)
Table 9.10 DMAC Internal Status
Item
SAR
DAR
DMATCR
Bus rights
DMAC operation
Interrupts
Transfer request source flag clear Executed
Notes: 1. Interrupts are executed until the DMATCR value becomes 0, and if the IE bit of the
To execute transfers after the fifth one when the address reload is on, make the transfer request
source issue another transfer request signal.
9.4.4
In this example, DMAC channel 3 is used, an indirect address designated external memory is the
transfer source and the SCI1 sending side is the transfer destination.
Table 9.11 indicates the transfer conditions and the setting values of each of the registers.
Rev. 5.00 Jan 06, 2006 page 192 of 818
REJ09B0273-0500
2. If transfer request source flag clears are executed until the DMATCR value becomes 0,
3. Designate burst mode when using the address reload function. There are cases where
4. Designate a multiple of four for the TCR value when using the address reload function.
Example of DMA Transfer between External Memory and SCI1 Send Side
(Indirect Address On)
CHCR is set to 1, are issued regardless of whether the address reload is on or off.
they are executed regardless of whether the address reload is on or off.
abnormal operation will result if it is executed in cycle steal mode.
There are cases where abnormal operation will result if anything else is designated.
Address Reload On
H'FFFF83F0
H'00400004
H'0000007C
Released
Halted
Not issued
Address Reload Off
H'FFFF83F4
H'00400004
H'0000007C
Maintained
Processing continues
Not issued
Not executed