HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 277

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 1—Input Capture/Compare-Match Interrupt Enable (IME2B): Enables or disables
interrupt requests by IMF2B in TSR when IMF2B is set to 1.
Bit 0—Input Capture/Compare-Match Interrupt Enable (IME2A): Enables or disables
interrupt requests by IMF2A in TSR when IMF2A is set to 1.
Timer Interrupt Enable Registers DH and DL (TIERDH, TIERDL)
TIERDH controls enabling/disabling of channel 3 input capture, compare-match, and overflow
interrupt requests.
Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 4—Overflow Interrupt Enable (OVE3): Enables or disables interrupt requests by OVF3 in
TSR when OVF3 is set to 1.
Bit 1:
IME2B
0
1
Bit 0:
IME2A
0
1
Bit 4:
OVE3
0
1
Initial value:
Description
IMI2B interrupt requested by IMF2B is disabled
IMI2B interrupt requested by IMF2B is enabled
Description
IMI2A interrupt requested by IMF2A is disabled
IMI2A interrupt requested by IMF2A is enabled
Description
OVI3 interrupt requested by OVF3 is disabled
OVI3 interrupt requested by OVF3 is enabled
R/W:
Bit:
—
R
7
0
—
R
6
0
—
R
5
0
OVE3
R/W
4
0
Rev. 5.00 Jan 06, 2006 page 257 of 818
Section 10 Advanced Timer Unit (ATU)
IME3D
R/W
3
0
IME3C
R/W
2
0
REJ09B0273-0500
IME3B
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
IME3A
R/W
0
0