HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 404

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Serial Communication Interface (SCI)
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode.
The MPBT setting is ignored in the clock synchronous mode, when a multiprocessor format is not
selected, or when the SCI is not transmitting.
Bit 0: MPBT
0
1
13.2.8
The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write the BRR. The BRR is initialized to H'FF by a power-on reset,
in hardware standby mode and software standby mode. Each channel has independent baud rate
generator control, so different values can be set in the two channels.
Table 13.3 lists examples of BRR settings in the asynchronous mode; table 13.4 lists examples of
BBR settings in the clock synchronous mode.
Rev. 5.00 Jan 06, 2006 page 384 of 818
REJ09B0273-0500
Initial value:
Bit Rate Register (BRR)
R/W:
Bit:
Description
Multiprocessor bit value in transmit data is 0 (initial value)
Multiprocessor bit value in transmit data is 1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1