HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 113

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

6.6
The following data transfers can be done using interrupt request signals:
Among interrupt sources, those designated as DMAC activating sources are masked and not input
to the INTC. The masking condition is listed below:
Figure 6.6 is a block diagram of interrupt controller.
Activate DMAC only, without generating CPU interrupt
M:
D:
E:
F:
Mask condition = DME • (DE0 • source selection 0 + DE1
source selection 2 + DE3 • source selection 3)
Data Transfer with Interrupt Request Signals
Interrupt service routine
Instruction fetch (instruction fetched from memory where program is stored).
Instruction decoding (fetched instruction is decoded).
Instruction execution (data operation and address calculation is performed
according to the results of decoding).
Memory access (data in memory is accessed).
Instruction (instruction
exception processing)
replaced by interrupt
start instruction
Figure 6.5 Pipeline when an IRQ Interrupt is Accepted
Overrun fetch
IRQ
1
Interrupt acceptance
3
F D
F
E E
3
5 + m1 + m2 + m3
Rev. 5.00 Jan 06, 2006 page 93 of 818
Section 6 Interrupt Controller (INTC)
m1 m2 1 m3 1
M M E
source selection 1 + DE2 •
M E E
REJ09B0273-0500
F D E