HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 467

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

14.3
A/D data registers 0 to 15 (ADDR0 to ADDR15) are 16-bit registers, but they are connected to the
CPU by an 8-bit data bus. Therefore, the upper and lower bytes must be read separately.
To prevent the data being changed between the reads of the upper and lower bytes of an A/D data
register, the lower byte is read via a temporary register (TEMP). The upper byte can be read
directly.
Data is read from an A/D data register as follows. When the upper byte is read, the upper-byte
value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the CPU.
When performing byte-size reads on an A/D data register, always read the upper byte before the
lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect
data may be obtained. If a word-size read is performed on an A/D data register, reading is
performed in upper byte, lower byte order automatically.
Figure 14.2 shows the data flow for access to an A/D data register.
Upper-byte read
Lower-byte read
CPU Interface
Figure 14.2 A/D Data Register Access Operation (Reading H'AA40)
(H'AA)
(H'40)
CPU
CPU
interface
interface
Bus
Bus
Rev. 5.00 Jan 06, 2006 page 447 of 818
ADDRnH
ADDRnH
(H'AA)
(H'AA)
Module data bus
Module data bus
Section 14 A/D Converter
ADDRnL
ADDRnL
TEMP
(H'40)
(H'40)
TEMP
(H'40)
(H'40)
REJ09B0273-0500