HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 89

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

5.5
5.5.1
Exception processing can be triggered by trap instructions, general illegal instructions, and illegal
slot instructions, as shown in table 5.8.
Table 5.8
5.5.2
When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
3. The exception service routine start address is fetched from the exception processing vector
Type
Trap instructions
Illegal slot
instructions
General illegal
instructions
instruction to be executed after the TRAPA instruction.
table that corresponds to the vector number specified in the TRAPA instruction. That address
is jumped to and the program starts executing. The jump that occurs is not a delayed branch.
Exceptions Triggered by Instructions
Types of Exceptions Triggered by Instructions
Trap Instructions
Types of Exceptions Triggered by Instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot)
and instructions that rewrite
the PC
Undefined code anywhere
besides in a delay slot
Comment
—
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
—
Rev. 5.00 Jan 06, 2006 page 69 of 818
Section 5 Exception Processing
REJ09B0273-0500