HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 274

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Advanced Timer Unit (ATU)
Bit 1—Input Capture Interrupt Enable (ICE0B): Enables or disables ICI0B requests when the
input capture flag (ICF0B) in TSR is set to 1.
Bit 1:
ICE0B
0
1
Bit 0—Input Capture Interrupt Enable (ICE0A): Enables or disables ICI0A requests when the
input capture flag (ICF0A) in TSR is set to 1.
Bit 0:
ICE0A
0
1
Timer Interrupt Enable Register B (TIERB)
TIERB controls enabling/disabling of channel 1 input capture, compare-match, and overflow
interrupt requests.
Bit 7—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 6—Overflow Interrupt Enable (OVE1): Enables or disables interrupt requests by OVF1 in
TSR when OVF1 is set to 1.
Bit 6:
OVE1
0
1
Rev. 5.00 Jan 06, 2006 page 254 of 818
REJ09B0273-0500
Initial value:
Description
ICI0B interrupt requested by ICF0B is disabled
ICI0B interrupt requested by ICF0B is enabled
Description
ICI0A interrupt requested by ICF0A is disabled
ICI0A interrupt requested by ICF0A is enabled
Description
OVI1 interrupt requested by OVF1 is disabled
OVI1 interrupt requested by OVF1 is enabled
R/W:
Bit:
—
R
7
0
OVE1
R/W
6
0
IME1F
R/W
5
0
IME1E
R/W
4
0
IME1D
R/W
3
0
IME1C
R/W
2
0
IME1B
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
IME1A
R/W
0
0