HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 483

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

15.2.2
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock
used for incrementation. It is initialized to H'0000 by a power-on reset and in hardware standby
mode and software standby mode.
Note:
Bits 15–8 and 5–2—Reserved: These bits always read as 0. The write value should always be 0.
Bit 7—Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and
CMCOR values have matched.
Bit 6—Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a
compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1).
Bit 7: CMF
0
1
Bit 6: CMIE
0
1
Initial value:
Initial value:
* The only value that can be written is a 0 to clear the flag.
Compare Match Timer Control/Status Register (CMCSR)
R/W:
R/W:
Bit:
Bit:
R/(W) *
CMF
15
—
R
0
7
0
Description
CMCNT and CMCOR values have not matched (initial status)
Clear condition: Write a 0 to CMF after reading a 1 from it
CMCNT and CMCOR values have matched
Description
Compare match interrupts (CMI) disabled (initial status)
Compare match interrupts (CMI) enabled
CMIE
R/W
14
—
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
Section 15 Compare Match Timer (CMT)
Rev. 5.00 Jan 06, 2006 page 463 of 818
11
—
—
R
R
0
3
0
10
—
—
R
R
0
2
0
REJ09B0273-0500
CKS1
R/W
—
R
9
0
1
0
CKS0
R/W
—
R
8
0
0
0