HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 449

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

13.5.7
13.5.8
13.5.9
When receiving, RDRF is 1 when RE is set to zero 1.5 clocks after the rising edge of the RxD D7
bit SCK output, but it cannot be copied to RDR.
When using an external clock source for the synchronization clock, update the TDR with the
DMAC, and then after five system clocks or more elapse, input a transmit clock. If a transmit
clock is input in the first four system clocks after the TDR is written, an error may occur
(figure 13.24).
Before reading the receive data register (RDR) with the DMAC, select the receive-data-full
interrupt of the SCI as a start-up source.
Set TE = RE = 1 only when the external clock SCK is 1.
Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed
from 0 to 1.
When receiving, RDRF is 1 when RE is set to zero 2.5–3.5 clocks after the rising edge of the
RxD D7 bit SCK input, but it cannot be copied to RDR.
TDRE
SCK
Note: During external clock operation, an error may occur if t is 4 or less.
Constraints on DMAC Use
Cautions for Clock Synchronous External Clock Mode
Caution for Clock Synchronous Internal Clock Mode
Figure 13.24 Example of Clock Synchronous Transmission with DMAC
t
D0
D1
D2
Section 13 Serial Communication Interface (SCI)
D3
Rev. 5.00 Jan 06, 2006 page 429 of 818
D4
D5
D6
REJ09B0273-0500
D7