HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 87

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

5.3.2
When an address error occurs, the bus cycle in which the address error occurred ends. When the
executing instruction then finishes, address error exception processing starts up. The CPU operates
as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
3. The exception service routine start address is fetched from the exception processing vector
5.4
5.4.1
Table 5.6 shows the sources that start up interrupt exception processing. These are divided into
NMI, user breaks, IRQ and on-chip peripheral modules.
Table 5.6
Each interrupt source is allocated a different vector number and vector table offset. See section 6,
Interrupt Controller, and table 6.3, Interrupt Exception Processing Vectors and Priorities, for more
information on vector numbers and vector table address offsets.
Type
NMI
User break
IRQ
On-chip peripheral module
instruction to be executed after the last executed instruction.
table that corresponds to the address error that occurred and the program starts executing from
that address. The jump that occurs is not a delayed branch.
Address Error Exception Processing
Interrupts
Interrupt Sources
Interrupt Sources
Request Source
NMI pin (external input)
User break controller
IRQ0–IRQ7 (external input)
Direct memory access controller (DMAC)
Advanced timer unit (ATU)
Compare match timer (CMT)
A/D converter
Serial communications interface (SCI)
Watchdog timer (WDT)
Rev. 5.00 Jan 06, 2006 page 67 of 818
Section 5 Exception Processing
REJ09B0273-0500
Number of
Sources
1
1
8
4
44
2
2
12
1