HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 142

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Bus State Controller (BSC)
8.2.5
The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM
area to be used when emulating realtime programming of flash memory.
RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not
initialized in software standby mode.
Note: To ensure correct operation of the RAM emulation function, the ROM for which RAM
Bits 15 to 3—Reserved: Only 0 should be written to these bits. Operation cannot be guaranteed if
1 is written.
Bit 2—RAM Select (RAMS): Used together with bits 1 and 0 to designate the RAM area (table
8.5 and table 8.6).
When 1 is written to this bit, all flash memory blocks are write/erase-protected.
This bit is ignored in modes with no on-chip ROM.
Bits 1 and 0—RAM Area Specification (RAM1, RAM0): These bits are used together with the
RAMS bit to designate the RAM area (tables 8.5 and 8.6).
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Initial value:
Initial value:
emulation is performed should not be accessed immediately after this register has been
modified. Operation cannot be guaranteed if such an access is made.
RAM Emulation Register (RAMER)
R/W:
R/W:
Bit:
Bit:
15
—
—
R
R
0
7
0
14
—
—
R
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
11
—
—
R
R
0
3
0
RAMS
R/W
10
—
R
0
2
0
RAM1
R/W
—
R
9
0
1
0
RAM0
R/W
—
R
8
0
0
0