HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 125

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

7.4
7.4.1
1. Register settings:
A user break interrupt will occur before the instruction at address H'00000404. If it is possible for
the instruction at H'00000402 to accept an interrupt, the user break exception processing will be
executed after execution of that instruction. The instruction at H'00000404 is not executed. The
PC value saved is H'00000404.
2. Register settings:
A user break interrupt does not occur because the instruction fetch cycle is not a write cycle.
3. Register settings:
A user break interrupt does not occur because the instruction fetch was performed for an even
address. However, if the first instruction fetch address after the branch is an odd address set by
these conditions, user break interrupt exception processing will be done after address error
exception processing.
Conditions set:
Conditions set:
Conditions set:
Use Examples
Break on CPU Instruction Fetch Cycle
UBARH = H'0000
UBARL = H'0404
UBBR = H'0054
Address: H'00000404
Bus cycle: CPU, instruction fetch, read
(operand size not included in conditions)
UBARH = H'0015
UBARL = H'389C
UBBR = H'0058
Address: H'0015389C
Bus cycle: CPU, instruction fetch, write
(operand size not included in conditions)
UBARH = H'0003
UBARL = H'0147
UBBR = H'0054
Address: H'00030147
Bus cycle: CPU, instruction fetch, read
(operand size not included in conditions)
Rev. 5.00 Jan 06, 2006 page 105 of 818
Section 7 User Break Controller (UBC)
REJ09B0273-0500