HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 347

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Sample Setup Procedure for PWM Timer Operation (Channels 6 to 9): An example of the
setup procedure for PWM timer operation (channels 6 to 9 ) is shown in figure 10.52.
1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1), and select the second-stage
2. Set the port B control register (PBCR) corresponding to the waveform output port to ATU
3. Set PWM waveform output 1 output timing in the cycle register (CYLR6–CYLR9), and set the
4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the TCNT counter for
Notes: 1. Do not make a setting in DTR after the counter is started. Use BFR to make a DTR
counter clock " with the CKSEL bit in the timer control register (TCR6–TCR9).
PWM output. Also set the corresponding bit to 1 in the port B IO register (PBIOR) to specify
the output attribute.
PWM waveform output 0 output timing in the buffer register (BFR6–BFR9) and duty register
(DTR6–DTR9). If necessary, an interrupt request can be sent to the CPU on a compare-match
between the CYLR value and the free-running counter (TCNT) value by making the
appropriate setting in the interrupt enable register (TIERE).
the relevant channel.
2. 0% duty is specified by setting H'0000 in the duty register (DTR), and 100% duty is
setting. For details, see section 10.3.10, Buffer Function.
specified by setting buffer register (BFR)
cycle register (CYLR).
Rev. 5.00 Jan 06, 2006 page 327 of 818
Section 10 Advanced Timer Unit (ATU)
REJ09B0273-0500