HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 632

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 ROM (256 kB Version)
Rev. 5.00 Jan 06, 2006 page 612 of 818
REJ09B0273-0500
Notes:
1. Transfer data in a byte unit. The lower eight bits of the start address to which data is written must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0.
2. Read verify data in logword form (32 bits).
3. Even for bits to which data is already written, an additional write should be performed if their verify result is NG.
4. The write data storage area (32 bytes) and rewrite data storage area (32 bytes) must be located in RAM. The contents of the rewrite data storage area are
Transfer 32-byte data even when writing fewer than 32 bytes. In this case, Set H'FF in unused addresses.
rewritten as writing progresses.
Source data (D)
Rewrite data storage area
Write data storage area
0
0
1
1
(32 byte)
(32 byte)
RAM
Increment address
Figure 19.7 Program/Program-Verify Flowchart
Verify data (V)
0
1
0
1
NG
Perform dummy-write H'FF to verify address
Rewrite data (X)
Transfer rewrite data to rewrite data area
Successively write 32-byte data in rewrite data
Clear PSU1 (2) bit in FLMCR1 (2)
Store 32 bytes write data in write
Clear PV1 (2) bit of FLMCR1 (2)
Set PSU1 (2) bit in FLMCR1 (2)
data area and rewrite data area
Clear P1 (2) bit in FLMCR1 (2)
Set PV1 (2) bit of FLMCR1 (2)
Set P1 (2) bit in FLMCR1 (2)
Clear SWE bit om FLMCR1
Set SWE-bit of FLMCR1
area in RAM to flash memory
Write data= Verify data?
1
0
1
1
Operate rewrite data
Read verify data
verify complete?
Disable WDT
Enable WDT
32 byte data
Wait 500 s
Wait 10 s
Wait 50 s
Wait 10 s
Wait 10 s
Wait
Wait 2 s
Wait 4 s
Write end
m = 0?
m = 0
n = 1
Start
Rewrite should not be performed to bits already written to.
Write is incomplete; rewrite should be performed.
—
Left in the erased state.
OK
OK
s
OK
Description
NG
NG
*4
*1
Write start
Write end
*2
*3
*4
m = 1
Data writes must be performed in the memory-
erased state. Do not write additional data to an
address to which data is already written.
Clear SWE bit in FLMCR1
Write failure
n
400?
OK
NG
n
n + 1