HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 548

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I/O Ports (I/O)
17.6.2
The port E data register (PEDR) is a 16-bit readable/writable register that stores port E data. Bits
PE14DR to PE0DR correspond to pins PE14/TIOC3 to PE0/TIOA1.
When a pin functions as a general output, if a value is written to PEDR, that value is output
directly from the pin, and if PEDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PEDR is read the pin state, not the register value, is
returned directly. If a value is written to PEDR, although that value is written into PEDR it does
not affect the pin state. Table 17.10 summarizes port E data register read/write operations.
PEDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
Table 17.10 Port E Data Register (PEDR) Read/Write Operations
PEIOR
0
1
Rev. 5.00 Jan 06, 2006 page 528 of 818
REJ09B0273-0500
Initial value:
R/W:
Bit:
Port E Data Register (PEDR)
Pin Function
General input
Other than general
input
General output
Other than general
output
15
—
R
1
PE14
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DR
14
0
PE13
DR
13
0
PE12
DR
12
0
PE11
Read
Pin state
Pin state
PEDR value
PEDR value
DR
11
0
PE10
DR
10
0
PE9
DR
9
0
Write
Value is written to PEDR, but does not affect
pin state
Value is written to PEDR, but does not affect
pin state
Write value is output from pin
Value is written to PEDR, but does not affect
pin state
PE8
DR
8
0
PE7
DR
7
0
PE6
DR
6
0
PE5
DR
5
0
PE4
DR
4
0
PE3
DR
3
0
PE2
DR
2
0
PE1
DR
1
0
PE0
DR
0
0