HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 68

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
Instruction
STS.L MACH,@–Rn
STS.L MACL,@–Rn
STS.L PR,@–Rn
TRAPA #imm
Note:
2.5
2.5.1
The CPU has five processing states: reset, exception processing, bus release, program execution
and power-down. Figure 2.6 shows the transitions between the states.
Rev. 5.00 Jan 06, 2006 page 48 of 818
REJ09B0273-0500
* The number of execution cycles before the chip enters sleep mode: The execution
Processing States
State Transitions
cycles shown in the table are minimums. The actual number of cycles may be
increased when (1) contention occurs between instruction fetches and data access, or
(2) when the destination register of the load instruction (memory
register used by the next instruction are the same.
Instruction Code
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Operation
Rn–4
Rn–4
Rn–4
PC/SR
PC
Rn, MACH
Rn, MACL
Rn, PR
stack area, (imm)
(Rn)
(Rn)
(Rn)
register) and the
Exec.
Cycles
1
1
1
8
T Bit
—
—
—
—