HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 749

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HD64F7050

Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Note:
Timer Status Register C (TSRC)
Bit
2
1
0
Initial value:
* Only 0 can be written to clear the flag.
Bit name:
Bit Name
Overflow flag (OVF2)
Input capture/compare
match flag (IMF2B)
Input capture/compare
match flag (IMF2A)
R/W:
Bit:
R
7
0
R
6
0
Value
0
1
0
1
0
1
R
5
0
H'FFFF82C9 (Channel 2)
Appendix A On-Chip Supporting Module Registers
Description
Read OVF2 when OVF2 =1, then write 0 in OVF2
[Setting condition]
TCNT2 overflowed from H'FFFF to H'0000
[Clearing condition]
Read IMF2B when IMF2B =1, then write 0 in
IMF2B
[Setting conditions]
1. TCNT2 value is transferred to GR2B by an
2. TCNT2 = GR2B when GR2B functions as an
[Clearing condition]
Read IMF2A when IMF2A =1, then write 0 in
IMF2A
[Setting conditions]
1. TCNT2 value is transferred to GR2A by an
2. TCNT2 = GR2A when GR2A functions as an
[Clearing condition]
input capture signal when GR2B functions as
an input capture register
output compare register
input capture signal when GR2A functions as
an input capture register
output compare register
R
4
0
Rev. 5.00 Jan 06, 2006 page 729 of 818
R
3
0
R/(W) *
OVF2
2
0
8
REJ09B0273-0500
R/(W) *
IMF2B
1
0
(Initial value)
(Initial value)
(Initial value)
R/(W) *
IMF2A
0
0
ATU

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