HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 353

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Contention between Interrupt Status Flag Setting by Interrupt Generation and Clearing: If
an event such as input capture/compare-match or overflow/underflow occurs in the T2 state of an
interrupt status flag 0 write cycle by the CPU, setting of the interrupt status flag to 1 by that event
has priority and the interrupt status flag is not cleared.
The timing in this case is shown in figure 10.57.
Figure 10.57 Contention between Interrupt Status Flag Setting by Compare-Match and
Compare-match signal
Internal write signal
Interrupt status flag
Address
TCNT
IMF
GR
CK
TSR write cycle
TSR address
Clearing
T1
N
Remains unchanged at 1
0 written
to TSR
T2
Rev. 5.00 Jan 06, 2006 page 333 of 818
Section 10 Advanced Timer Unit (ATU)
N
N + 1
REJ09B0273-0500