HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 91

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

5.6
When an address error or interrupt is generated after a delayed branch instruction or interrupt-
disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in
table 5.9. When this happens, it will be accepted when an instruction that can accept the exception
is decoded.
Table 5.9
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
5.6.1
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,
neither address errors nor interrupts are accepted. The delayed branch instruction and the
instruction located immediately after it (delay slot) are always executed consecutively, so no
exception processing occurs during this period.
5.6.2
When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts
are not accepted. Address errors are accepted.
Point of Occurrence
Immediately after a delayed branch instruction *
Immediately after an interrupt-disabled instruction *
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
When Exception Sources Are Not Accepted
Immediately after a Delayed Branch Instruction
Immediately after an Interrupt-Disabled Instruction
BRAF
Generation of Exception Sources Immediately after a Delayed Branch
Instruction or Interrupt-Disabled Instruction
1
2
Rev. 5.00 Jan 06, 2006 page 71 of 818
Address Error
Not accepted
Accepted
Section 5 Exception Processing
Exception Source
Interrupt
Not accepted
Not accepted
REJ09B0273-0500