HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 151

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Bus State Controller (BSC)
8.5
Bus Arbitration
The SH7050 series has a bus arbitration function that, when a bus release request is received from
an external device, releases the bus to that device. It also has two internal bus masters, the CPU
and the DMAC, DTC. The priority ranking for determining bus right transfer between these bus
masters is:
Bus right request from external device > DMAC > CPU
Therefore, an external device that generates a bus request is given priority even if the request is
made during a DMAC burst transfer.
A bus request by an external device should be input at the BREQ pin. The signal indicating that
the bus has been released is output from the BACK pin.
Figure 8.9 shows the bus right release procedure.
SH7050 series
External device
BREQ = Low
BREQ accepted
Bus right request
Strobe pin:
high-level output
Address, data,
BACK confirmation
strobe pin:
high impedance
BACK = Low
Bus right release
response
Bus right release status
Bus right acquisition
Figure 8.9 Bus Right Release Procedure
Rev. 5.00 Jan 06, 2006 page 131 of 818
REJ09B0273-0500