HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 131

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

8.1.3
Table 8.1 shows the bus state controller pin configuration.
Table 8.1
Note: When an 8-bit bus width is selected for external space, WRL is enabled.
8.1.4
The BSC has eight registers. These registers are used to control wait states, bus width, and
interfaces with memories like ROM and SRAM, as well as refresh control. The register
configurations are listed in table 8.2.
All registers are 16 bits. All BSC registers are all initialized by a power-on reset, but are not by a
manual reset. Values are maintained in standby mode.
Signal
A21–A0
D15–D0
CS0–CS3
RD
WRH
WRL
WAIT
BREQ
BACK
When a 16-bit bus width is selected for external space, WRH and WRL are enabled.
Pin Configuration
Register Configuration
Pin Configuration
I/O
O
I/O
O
O
O
O
I
I
O
Description
Address output
16-bit data bus.
Chip select, indicating the area being accessed
Strobe that indicates the read cycle for ordinary space/multiplex I/O.
Strobe that indicates a write cycle to the 3rd byte (D15–D8) for ordinary
space/multiplex I/O. Also output during DRAM access.
Strobe that indicates a write cycle to the least significant byte (D7–D0) for
ordinary space/multiplex I/O. Also output during DRAM access.
Wait state request signal
Bus release request input
Bus use enable output
Rev. 5.00 Jan 06, 2006 page 111 of 818
Section 8 Bus State Controller (BSC)
REJ09B0273-0500