HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 355

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input
Capture/Compare-Match: If a clear request signal is generated by the DMAC when the interrupt
status flag (ICF0B, CMF6) is set by input capture (ICR0B) or compare-match (CYLR6), clearing
by the DMAC has priority and the interrupt status flag is not set.
The width of the DMAC clear request signal is normally two states, the same as an ATU access
cycle, and clearing is performed in two states. If a bus wait, or a bus request from off-chip, occurs
while the DMAC clear request signal is being output, the DMAC clear request signal width will be
N states (N
The timing in this case is shown in figure 10.59
Figure 10.59 Contention between Interrupt Status Flag Clearing by DMAC and Setting by
a. When the input capture/compare-match signal precedes the interrupt status flag
b. When the input capture/compare-match signal follows the interrupt status flag
3).
compare-match signal
clear signal by 1/2 state
clear signal by 1/2 state, and contention arises
compare-match signal
DMAC clear request
DMAC clear request
Interrupt status flag
Interrupt status flag
Interrupt status flag
Interrupt status flag
Input capture/
ICF0B, CMF6
Input capture/
ICF0B, CMF6
clear signal
clear signal
signal
signal
Input Capture/Compare-Match
CK
CK
1/2 state
Rev. 5.00 Jan 06, 2006 page 335 of 818
Section 10 Advanced Timer Unit (ATU)
REJ09B0273-0500