HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 88

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Exception Processing
5.4.2
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously
(overlap), the interrupt controller (INTC) determines their relative priorities and starts up
processing according to the results.
The priority order of interrupts is expressed as priority levels 0–16, with priority 0 the lowest and
priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always
accepted. The user break interrupt priority level is 15. IRQ interrupts and on-chip peripheral
module interrupt priority levels can be set freely using the INTC’s interrupt priority level setting
registers A through H (IPRA to IPRH) as shown in table 5.7. The priority levels that can be set are
0–15. Level 16 cannot be set.
Table 5.7
Type
NMI
User break
IRQ
On-chip peripheral module
5.4.3
When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI
is always accepted, but other interrupts are only accepted if they have a priority level higher than
the priority level set in the interrupt mask bits (I3–I0) of the status register (SR).
When an interrupt is accepted, exception processing begins. In interrupt exception processing, the
CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted
interrupt is written to SR bits I3–I0. For NMI, however, the priority level is 16, but the value set in
I3–I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the
exception processing vector table for the accepted interrupt, that address is jumped to and
execution begins.
Rev. 5.00 Jan 06, 2006 page 68 of 818
REJ09B0273-0500
Interrupt Priority Level
Interrupt Exception Processing
Interrupt Priority Order
Priority Level
16
15
0–15
0–15
Comment
Fixed priority level. Cannot be masked.
Fixed priority level.
Set with interrupt priority level setting registers A
through H (IPRA to IPRH).
Set with interrupt priority level setting registers A
through H (IPRA to IPRH).