HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 229

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HD64F7050

Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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10.1.4
Figure 10.10 shows the first and second prescaler stages in the ATU. The output of the first
prescaler stage is input to channel 0. Either the output of the second prescaler stage or an external
clock can be input to channels 1 to 10, and an additional external clock (TCLKA or TCLKB) can
be input to channels 1 to 5.
prescaler control register 1 (PSCR1).
in the timer control register (TCR).
/m (1
/2
n
(0
Input clock
Settable prescaler values
n
m
Prescaler Diagram
5) can be set as the output of the second prescaler stage ( "), the setting being made
32) can be set as the output of the first prescaler stage ( '), the setting being made in
or external clock
' = /m (1
" = '/2
" = '/2
First prescaler
stage setting
1
PSCR1
register
' = ø/m
n
n
m
(0
(0
m
32
n
n
32)
5)
5)
Figure 10.10 Prescaler Diagram
'
Second prescaler
stage setting
register
TCR10
TCR1
TCR2
TCR3
TCR4
TCR5
TCR6
TCR7
TCR8
TCR9
Rev. 5.00 Jan 06, 2006 page 209 of 818
Section 10 Advanced Timer Unit (ATU)
external clock
external clock
external clock
external clock
external clock
" or
" or
" or
" or
" or
"
"
"
"
"
DCNT10A–DCNT10F
DCNT10G, DCNT10H
Channel 10
Channel 10
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 9
REJ09B0273-0500

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