HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 147

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

8.3.3
Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period
beyond the length of the CSn signal assert period by setting the SW3–SW0 bits of BCR2. This
allows for flexible interfaces with external circuitry. The timing is shown in figure 8.6. T
cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these
cycles; RD and WRx signals are not. Further, data is extended up to the T
effective for gate arrays and the like, which have slower write operations.
Read
Write
CS Assert Period Extension
CS
CS
CS
Address
WRx
Data
Data
CSn
RD
CK
Figure 8.6 CS
T
h
CS Assert Period Extension Function
CS
CS
T
1
Rev. 5.00 Jan 06, 2006 page 127 of 818
T
Section 8 Bus State Controller (BSC)
2
T
f
f
cycle, which is
REJ09B0273-0500
h
and T
f