LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 1033

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array

read access from the CPU or XGATE.

CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not

Freescale Semiconductor

Offset Module Base + 0x0004

ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is

being read. See

Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command

has completed.

0 Command complete interrupt disabled

1 An interrupt will be requested whenever the CCIF ﬂag in the FSTAT register is set (see

Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see

0 All single bit faults detected during array reads are reported

1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be

Flash Conﬁguration Register (FCNFG)

= Unimplemented or Reserved

Section 27.3.2.13, “Flash ECC Error Results Register

Figure 27-9. Flash Conﬁguration Register (FCNFG)

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 27-14. FECCRIX Field Descriptions

Table 27-15. FCNFG Field Descriptions

Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)

(FECCR),” for more details.