LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 226

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 3 Memory Mapping Control (S12XMMCV4)

In emulation single-chip mode the external bus is connected to the emulator. If the EROMON bit is set,

the internal FLASH provides the data and the emulator can observe all internal CPU actions on the external

bus. If the EROMON bit is cleared, the emulator provides the data (generator) and traces the all CPU

actions (see

In normal expanded mode the external bus will be connected to the application. If the ROMON bit is set,

the internal FLASH provides the data. If the ROMON bit is cleared, the application memory provides the

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

ROM Control in Emulation Single-Chip Mode

ROM Control in Normal Expanded Mode

Figure 3-25. ROM in Emulation Single-Chip Mode

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 3-24. ROM in Single Chip Modes

No External Bus

Freescale Semiconductor