LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 477

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read: Anytime
Write: Anytime except if PLLSEL = 1
11.3.2.4
This register provides S12XECRG status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
Freescale Semiconductor
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset.
Module Base + 0x0002
Module Base + 0x0003
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
W
R
R
f PLL
RTIF
S12XECRG Flags Register (CRGFLG)
0
0
0
7
7
=
If POSTDIV = $00 then f
------------------------------------- -
(
2xPOSTDIV
f VCO
= Unimplemented or Reserved
= Unimplemented or Reserved
Note 1
PORF
Figure 11-5. S12XECRG Post Divider Register (POSTDIV)
0
0
6
6
Figure 11-6. S12XECRG Flags Register (CRGFLG)
)
MC9S12XE-Family Reference Manual Rev. 1.23
Note 2
LVRF
5
0
0
5
PLL
is identical to f
LOCKIF
Note 3
NOTE
0
4
4
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
VCO
LOCK
0
0
3
3
(divide by one).
POSTDIV[4:0]
ILAF
2
0
2
0
SCMIF
0
0
1
1
SCM
0
0
0
0
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