LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 265

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6
Interrupt (S12XINTV2)
6.1
The XINT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to either the CPU or the XGATE module. The XINT module supports:
Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a
flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority
scheme can be used to implement nested interrupt capability where interrupts from a lower level are
automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be
handled by the XGATE module can be nested one level deep.
Freescale Semiconductor
Revision
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Number
V02.00
V02.04
V02.05
V02.06
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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I bit and X bit maskable interrupt requests
One non-maskable unimplemented op-code trap
One non-maskable software interrupt (SWI) or background debug mode request
One non-maskable system call interrupt (SYS)
Three non-maskable access violation interrupt
One spurious interrupt vector request
Three system reset vector requests
Introduction
Revision Date
20 Mar 2007
11 Jan 2007
07 Jan 2008
01 Jul 2005
The HPRIO register and functionality of the original S12 interrupt module
is no longer supported, since it is superseded by the 7-level interrupt request
priority scheme.
6.3.2.2/6-271
6.3.2.4/6-272
6.1.2/6-266
6.4.6/6-278
6.1.2/6-266
Sections
Affected
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 6-1. Revision History
Initial V2 release, added new features:
- XGATE threads can be interrupted.
- SYS instruction vector.
- Access violation interrupt vectors.
- Added Notes for devices without XGATE module.
- Fixed priority definition for software exceptions.
- Added clarification of “Wake-up from STOP or WAIT by XIRQ with X bit set”
feature.
NOTE
Description of Changes
265