LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 412

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 10 XGATE (S12XGATEV3)
BITL
Operation
RD.L & IMM8 ⇒ NONE
Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant.
Only the condition code flags get updated, but no result is written
CCR Effects
Code and CPU Cycles
412
N:
Z:
V:
C:
BITL RD, #IMM8
N
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 7 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Z
0
V
Source Form
C
MC9S12XE-Family Reference Manual , Rev. 1.23
Bit Test Immediate 8 bit Constant
Address
Mode
IMM8
1
(Low Byte)
0
0
1
0
Machine Code
RD
back.
IMM8
Freescale Semiconductor
BITL
Cycles
P

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