LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 75

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The clock and reset generator module (CRG) provides the internal clock signals for the core and all

peripheral modules.

Consult the CRG speciﬁcation for details on clock generation.

The system clock can be supplied in several ways enabling a range of system operating frequencies to be

The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and

bus clock. As shown in

the memories, and the peripherals.

Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

The on-chip phase locked loop (PLL)

the PLL self clocking

the oscillator

System Clock Description

SCI0 . . SCI 7

SPI0 . . SPI2

1-9, these system clocks are used throughout the MCU to drive the core,

shows the clock connections from the CRG to all modules.

MC9S12XE-Family Reference Manual Rev. 1.23

Figure 1-9. Clock Connections

CAN0 . . CAN4

Oscillator Clock

Chapter 1 Device Overview MC9S12XE-Family