LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 826

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 23 Voltage Regulator (S12VREGL3V3V1)

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Autonomous Periodical Interrupt Rate Bits — These bits deﬁne the timeout period of the API. See

VREGAPICL register.

Figure 23-6. Autonomous Periodical Interrupt Rate High Register (VREGAPIRH)

Figure 23-7. Autonomous Periodical Interrupt Rate Low Register (VREGAPIRL)

for details of the effect of the autonomous periodical interrupt rate bits. Writable only if APIFE = 0 of

= Unimplemented or Reserved

Table 23-9. Selectable Autonomous Periodical Interrupt Periods

Table 23-8. VREGAPIRH / VREGAPIRL Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

131068 * bus clock period

131070 * bus clock period

10 * bus clock period

12 * bus clock period

2 * bus clock period

4 * bus clock period

6 * bus clock period

8 * bus clock period

Selected Period

Freescale Semiconductor