LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 712

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)

The scaled A clock uses clock A as an input and divides it further with a user programmable value and

then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user

programmable value and then divides this by 2. The rates available for clock SA are software selectable to

be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock

MC9S12XE-Family Reference Manual , Rev. 1.23

Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010