LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 148

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.54
2.3.55
148
Address 0x0261
Address 0x0262
Write:Never, writes to this register have no effect.
Field
Field
PTIH
PTH
PTH
Reset
Reset
7-0
1
0
W
W
R
R
Port H general purpose input/output data—Data Register
Port H pin 1 is associated with the TXD signal of the SCI6 module and the MOSI signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI6 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI6 function takes precedence over the general purpose I/O function if the SCI6 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 0 is associated with the RXD signal of the SCI6 module and the MISO signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI6 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI6 function takes precedence over the general purpose I/O function if the SCI6 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
DDRH7
PTIH7
Port H Input Register (PTIH)
Port H Data Direction Register (DDRH)
u
0
7
7
= Unimplemented or Reserved
DDRH6
PTIH6
Table 2-49. PTH Register Field Descriptions (continued)
u
0
6
6
Figure 2-53. Port H Data Direction Register (DDRH)
Table 2-50. PTIH Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-52. Port H Input Register (PTIH)
DDRH5
PTIH5
u
0
5
5
DDRH4
PTIH4
u
0
4
4
Description
Description
u = Unaffected by reset
DDRH3
PTIH3
3
u
3
0
DDRH2
PTIH2
u
0
2
2
Access: User read/write
Freescale Semiconductor
DDRH1
PTIH1
u
0
1
1
Access: User read
DDRH0
PTIH0
u
0
0
0
(1)
(1)