LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 731

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.2.2
Read: Anytime, if AMAP = 0.
Write: Anytime, if AMAP = 0.
Freescale Semiconductor
Module Base + 0x0002
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
SCISWAI
LOOPS
Reset
RSRC
WAKE
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
M
7
6
5
4
3
W
R
LOOPS
Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI
and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must
be enabled to use the loop function.
0 Normal operation enabled
1 Loop operation enabled
The receiver input is determined by the RSRC bit.
SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.
0 SCI enabled in wait mode
1 SCI disabled in wait mode
Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register
input. See
0 Receiver input internally connected to transmitter output
1 Receiver input connected externally to transmitter
Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.
0 One start bit, eight data bits, one stop bit
1 One start bit, nine data bits, one stop bit
Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the
most significant bit position of a received data character or an idle condition on the RXD pin.
0 Idle line wakeup
1 Address mark wakeup
SCI Control Register 1 (SCICR1)
0
7
This register is only visible in the memory map if AMAP = 0 (reset
condition).
Table
SCISWAI
0
6
20-5.
TNP[1:0]
Figure 20-5. SCI Control Register 1 (SCICR1)
11
10
01
00
MC9S12XE-Family Reference Manual Rev. 1.23
Table 20-3. IRSCI Transmit Pulse Width
Table 20-4. SCICR1 Field Descriptions
RSRC
5
0
NOTE
M
0
4
Narrow Pulse Width
Description
WAKE
1/32
1/16
3/16
1/4
Chapter 20 Serial Communication Interface (S12SCIV5)
0
3
ILT
2
0
PE
0
1
PT
0
0
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