LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 252

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 External Bus Interface (S12XEBIV4)
5.4
This section describes the functions of the external bus interface. The availability of external signals and
functions in relation to the operating mode is initially summarized and described in more detail in separate
sub-sections.
5.4.1
A summary of the external bus interface functions for each operating mode is shown in
252
EXSTR1[2:0]
EXSTR0[2:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
unimplemented area
visible externally
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
address access
Internal access
Field
PRR access
6–4
2–0
(if Enabled)
Properties
access
External
and
Functional Description
Operating Modes and External Bus Properties
(2)
External Access Stretch Option 1 Bits 2, 1, 0 — This three bit field determines the amount of additional clock
stretch cycles on every access to the external address space as shown in
External Access Stretch Option 0 Bits 2, 1, 0 — This three bit field determines the amount of additional clock
stretch cycles on every access to the external address space as shown in
(1)
write internal
Single-Chip
read internal
2 cycles
Normal
Single-Chip Modes
—
—
Table 5-8. External Access Stretch Bit Definition
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 5-7. EBICTL1 Field Descriptions
EXSTRx[2:0]
Table 5-9. Summary of Functions
write internal
Single-Chip
read internal
2 cycles
Special
000
001
010
011
100
101
110
111
—
—
Timing Properties
Max. of 2 to 9
or n cycles of
write internal
read internal
programmed
Number of Stretch Cycles
Expanded
ext. wait
2 cycles
Normal
cycles
Description
—
(3)
1
2
3
4
5
6
7
8
write int & ext
read external
Single-Chip
Emulation
2 cycles
1 cycle
1 cycle
Expanded Modes
Table
Table
Max. of 2 to 9
write int & ext
read external
or n cycles of
programmed
5-8.
5-8.
Emulation
Expanded
ext. wait
2 cycles
1 cycle
cycles
Freescale Semiconductor
3
Table
write internal
read internal
5-9.
2 cycles
Special
1 cycle
1 cycle
Test