LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 721

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the
corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order
bytes PWMEx bits have no effect and their corresponding PWM output is disabled.
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Clock Source 7
Clock Source 5
Clock Source 3
Clock Source 1
MC9S12XE-Family Reference Manual Rev. 1.23
Figure 19-24. PWM 16-Bit Mode
PWMCNT6
PWMCNT4
PWMCNT2
PWMCNT0
High
High
High
High
Period/Duty Compare
Period/Duty Compare
Period/Duty Compare
Period/Duty Compare
PWCNT7
PWCNT5
PWCNT3
PWCNT1
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
Low
Low
Low
Low
PWM7
PWM5
PWM3
PWM1
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