LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 728

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 20 Serial Communication Interface (S12SCIV5)
20.2
The SCI module has a total of two external pins.
20.2.1
The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high
impedance anytime the transmitter is disabled.
20.2.2
The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is
ignored when the receiver is disabled and should be terminated to a known voltage.
20.3
This section provides a detailed description of all the SCI registers.
20.3.1
The memory map for the SCI module is given below in
the address offset. The total address for each register is the sum of the base address for the SCI module and
the address offset for each register.
728
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
External Signal Description
Memory Map and Register Definition
TXD — Transmit Pin
RXD — Receive Pin
Module Memory Map and Register Definition
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure
20-2. The address listed for each register is
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