LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 382

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
10.6.1.0.1
Debug mode can be entered in four ways:
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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1. Setting XGDBG to "1"
Single Stepping
Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core
registers will be updated accordingly.
Write accesses to the XGCHID register and the XGCHPL register
XGATE threads can be initiated and terminated through a 16 write access to the XGCHID and the
XGCHPL register or through a 8 bit write access to the XGCHID register. Detailed operation is
shown in
can be executed by leaving debug mode.
1. 8 bit write access to XGCHID
XGCHID
1..127
1..127
Register Content
0
0
Even though zero is not a valid interrupt priority level of the S12X_INT
module, a thread of priority level 0 can be initiated in debug mode. The
XGATE handles requests of priority level 0 in the same way as it handles
requests of priority levels 1 to 3.
All channels 1 to 127 can be initiated by writing to the XGCHID register,
even if they are not assigned to any peripheral module.
In Debug Mode the XGATE will ignore all requests from peripheral
modules.
Entering Debug Mode
Table
Table 10-22. Initiating and Terminating Threads in Debug Mode
XGCHPL
10-22. Once a thread has been initiated it’s code can be either single stepped or it
All other combinations
0..3
0..7
0
0
MC9S12XE-Family Reference Manual , Rev. 1.23
XGCHID
1..127
1..127
1..127
Single Cycle Write
0
Access to...
XGCHPL
NOTE
NOTE
NOTE
0..7
4..7
0..7
-
-
(1)
1
Resume interrupted thread or become idle if
no interrupted thread is pending
Terminate current thread.
Interrupt current thread
Set XGCHPL to 0x01
Initiate new thread
Initiate new thread
Initiate new thread
Set new XGCHPL
Set new XGCHPL
Set new XGCHID
Set new XGCHID
Set new XGCHID
No action
Action
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