LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 324

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8 S12X Debug (S12XDBGV3) Module
Write: If DBG not armed. See
The DBGC1_COMRV bits determine which comparator control, address, data and datamask registers are
visible in the 8-byte window from 0x0028 to 0x002F as shown in
324
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
(Comparators
(Comparators
(Comparators
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
B and D)
B and D)
COMRV
A and C
Field
RWE
NDB
BRK
SZE
TAG
RW
SZ
00
01
10
11
7
6
6
5
4
3
2
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the
associated comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
register value or when the data bus differs from the register value. Furthermore data bus bits can be
individually masked using the comparator data mask registers. This bit is only available for comparators A
and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality for
comparators B and D.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
This bit position has NDB functionality for comparators A and C
0 Word access size will be compared
1 Byte access size will be compared
Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the
matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.
0 Trigger immediately on match
1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated
Break — This bit controls whether a channel match terminates a debug session immediately, independent
of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled
using DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator . The RW bit is not used if RWE = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator. This bit is not used for tagged operations.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
tracing, if active, is terminated and the module disarmed.
DBGCCTL, DBGCAH, DBGCAM, DBGCAL, DBGCDH, DBGCDL, DBGCDHM, DBGCDLM
DBGACTL, DBGAAH ,DBGAAM, DBGAAL, DBGADH, DBGADL, DBGADHM, DBGADLM
Table 8-29. Comparator Address Register Visibility
Table 8-29
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 8-30. DBGXCTL Field Descriptions
DBGDCTL, DBGDAH, DBGDAM, DBGDAL
DBGBCTL, DBGBAH, DBGBAM, DBGBAL
for visible register encoding.
Visible Comparator
Description
Section Table 8-29.
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