LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 825

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.3.2.4
The VREGAPITR register allows to trim the API timeout period.
23.3.2.5
The VREGAPIRH and VREGAPIRL register allows the configuration of the VREG_3V3 autonomous
periodical interrupt rate.
Freescale Semiconductor
0x02F3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
APITR[5:0]
1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
APIE
APIF
Field
7–2
1
0
W
R
APITR5
Autonomous Periodical Interrupt Enable Bit
0 API interrupt request is disabled.
1 API interrupt will be requested whenever APIF is set.
Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API configured time has elapsed.
This flag can only be cleared by writing a 1 to it. Clearing of the flag has precedence over setting.
Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request.
0 API timeout has not yet occurred.
1 API timeout has occurred.
Autonomous Periodical Interrupt Period Trimming Bits — See
Autonomous Periodical Interrupt Trimming Register (VREGAPITR)
0
Autonomous Periodical Interrupt Rate High and Low Register
(VREGAPIRH / VREGAPIRL)
Figure 23-5. Autonomous Periodical Interrupt Trimming Register (VREGAPITR)
7
1
= Unimplemented or Reserved
APITR4
APITR[5]
APITR[4]
APITR[3]
APITR[2]
APITR[1]
APITR[0]
Table 23-5. VREGAPICL Field Descriptions (continued)
0
6
1
Bit
Table 23-6. VREGAPITR Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.23
Table 23-7. Trimming Effect of APIT
Increases period
Decreases period less than APITR[5] increased it
Decreases period less than APITR[4]
Decreases period less than APITR[3]
Decreases period less than APITR[2]
Decreases period less than APITR[1]
APITR3
0
5
1
APITR2
0
4
1
Trimming Effect
Description
Description
APITR1
0
3
1
Chapter 23 Voltage Regulator (S12VREGL3V3V1)
Table 23-7
APITR0
0
2
1
for trimming effects.
0
0
1
0
0
0
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