LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 751

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control
register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
20.4.6.3
The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust
for baud rate mismatch, the RT clock (see
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic
1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Figure 20-17
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
RT CLock Count
•
•
Reset RT Clock
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
RT Clock
Samples
RXD
Data Sampling
summarizes the results of the start bit verification samples.
1
RT3, RT5, and RT7 Samples
1
1
1
000
001
010
011
100
101
110
111
1
MC9S12XE-Family Reference Manual Rev. 1.23
1
Figure 20-21. Receiver Data Sampling
Qualification
Start Bit
Table 20-17. Start Bit Verification
1
1
Figure
0
0
20-21) is re-synchronized:
Start Bit Verification
Verification
Start Bit
0
Yes
Yes
Yes
Yes
No
No
No
No
0
Chapter 20 Serial Communication Interface (S12SCIV5)
Start Bit
0
Sampling
Data
0
0
Noise Flag
0
1
1
0
1
0
0
0
LSB
751