LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 1245

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Freescale Semiconductor

See Figure A-9.

the timing characteristics for master mode are listed.

SCK frequency

Enable lead time

Enable lag time

Clock (SCK) high or low time

Data setup time (inputs)

Data hold time (inputs)

Data valid after SCK edge

Data valid after SS fall (CPHA = 0)

Data hold time (outputs)

Rise and fall time inputs

Rise and fall time outputs

Figure A-9. Derating of maximum f

Table A-28. SPI Master Mode Timing Characteristics

Characteristic

MC9S12XE-Family Reference Manual Rev. 1.23

ratio in Master Mode

Appendix A Electrical Characteristics