LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 537

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Read or write: Anytime

All bits reset to zero.

Freescale Semiconductor

Module Base + 0x0000

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Input Capture or Output Compare Channel Conﬁguration

0 The corresponding channel acts as an input capture.

1 The corresponding channel acts as an output compare.

Timer Input Capture/Output Compare Select Register (TIOS)

Figure 14-3. Timer Input Capture/Output Compare Register (TIOS)

= Unimplemented or Reserved

Figure 14-2. ECT Register Summary (Sheet 5 of 5)

MC9S12XE-Family Reference Manual Rev. 1.23

Table 14-2. TIOS Field Descriptions

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)