LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 754

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 20 Serial Communication Interface (S12SCIV5)
In
at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived
bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
Figure 20-25
synchronization with the start bit time, it does set the noise flag.
754
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Figure
RT Clock Count
Reset RT Clock
RT Clock Count
Reset RT Clock
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
RT Clock
RT Clock
Samples
Samples
20-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample
RXD
RXD
shows the effect of noise early in the start bit time. Although this noise does not affect proper
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1
0
1
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 20-24. Start Bit Search Example 3
Figure 20-25. Start Bit Search Example 4
1
0
1
1
1
1
Perceived Start Bit
0
0
0
1
0
0
Perceived and Actual Start Bit
0
Actual Start Bit
Freescale Semiconductor
LSB
LSB