LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 181

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Always reads 0x00
1. Read: Anytime.
2.3.106 Port F Polarity Select Register (PPSF)
2.3.107 PIM Reserved Register
2.3.108 Port F Routing Register (PTFRR)
Freescale Semiconductor
Address 0x037D
Address 0x037E
Address 0x037F
Write: Anytime.
Write: Unimplemented
Write: Anytime.
PPSF
Field
Reset
Reset
Reset
7-0
W
W
W
R
R
R
Port F pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
PPSF7
0
0
0
0
0
7
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
PPSF6
0
0
0
0
0
6
6
6
Figure 2-104. Port F Polarity Select Register (PPSF)
Figure 2-106. Port F Routing Register (PTFRR)
Table 2-101. PPSF Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-105. PIM Reserved Register
PTFRR5
PPSF5
0
0
0
0
5
5
5
PTFRR4
PPSF4
0
0
0
0
4
4
4
Description
PTFRR3
PPSF3
3
0
3
0
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PTFRR2
PPSF2
0
0
0
0
2
2
2
Access: User read/write
Access: User read/write
PTFRR1
PPSF1
0
0
0
0
1
1
1
Access: User read
PTFRR0
PPSF0
0
0
0
0
0
0
0
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