LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 734

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 20 Serial Communication Interface (S12SCIV5)

Read: Anytime, if AMAP = 1

Write: Anytime, if AMAP = 1

Module Base + 0x0001

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt ﬂag,

RXEDGIF, to generate interrupt requests.

0 RXEDGIF interrupt requests disabled

1 RXEDGIF interrupt requests enabled

Bit Error Interrupt Enable — BERRIE enables the bit error interrupt ﬂag, BERRIF, to generate interrupt

0 BERRIF interrupt requests disabled

1 BERRIF interrupt requests enabled

Break Detect Interrupt Enable — BKDIE enables the break detect interrupt ﬂag, BKDIF, to generate interrupt

0 BKDIF interrupt requests disabled

1 BKDIF interrupt requests enabled

SCI Alternative Control Register 1 (SCIACR1)

= Unimplemented or Reserved

Figure 20-7. SCI Alternative Control Register 1 (SCIACR1)

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 20-7. SCIACR1 Field Descriptions

Freescale Semiconductor